1. Technical Field
The present invention relates to a precharge circuit of a semiconductor memory apparatus, and more particularly, to a precharge circuit of a semiconductor memory apparatus that precharges a pair of local input/output lines LIO and LIOb.
2. Related Art
A conventional precharge circuit of a semiconductor memory apparatus will now be described with reference to FIGS. 1 to 3.
FIG. 1 is a circuit diagram of a conventional precharge circuit of a semiconductor memory apparatus.
The conventional precharge circuit of a semiconductor memory apparatus includes a first PMOS transistor P1, a second PMOS transistor P2 and a third PMOS transistor P3.
The first PMOS transistor P1 and a second PMOS transistor P2 precharge a pair of local input/output lines LIO and LIOb to a core voltage VCORE1 in response to a precharge signal LIOEQb.
The third PMOS transistor P3 equalizes the pair of local input/output lines LIO and LIOb in response to the precharge signal LIOEQb.
The pair of local input/output lines LIO and LIOb comprise of a local input/output line LIO and an inverted local input/output line LIOb that has an inverted level with respect to the level of the local input/output line LIO.
As shown in FIG. 1, the first PMOS transistor P1 receives the precharge signal LIOEQb at its gate terminal and its source and drain terminals are coupled between the local input/output line LIO and an input terminal of the core voltage VCORE1.
The second PMOS transistor P2 is connected to the precharge signal LIOEQb at its gate terminal and its source and drain terminals are coupled between the input terminal of the core voltage VCORE1 and the inverted local input/output line LIOb.
The third PMOS transistor P3 is connected to the precharge signal LIOEQb at its gate terminal and its source and drain terminals are coupled between the local input/output lines LIO and the inverted local input/output line LIOb.
The core voltage VCORE1 is an internal voltage having a target level of a core voltage VCORE1, which is generated from an external supply voltage VDD by comparing a divided voltage level of the external supply voltage VDD with a reference voltage VREF1. The core voltage VCORE1 is used to precharge the pair of local input/output lines LIO and LIOb.
The pair of local input/output lines LIO and LIOb are coupled to a pair of global data lines GIO and GIOb through an input/output sense amplifier (hereinafter, referred to as an IO S/A) and are used to input/output data in a bank region of a semiconductor memory apparatus.
FIG. 2 is a waveform chart illustrating a conventional core voltage.
As shown in FIG. 2, even though the external supply voltage VDD rises, the core voltage VCORE1 is held at a constant level (a target level of the core voltage VCORE1).
The conventional precharge circuit of a semiconductor memory apparatus will now be described with reference to FIGS. 1 and 2.
When the precharge signal LIOEQb is enabled at a logic low level, the first to third PMOS transistor P1, P2 and P3 are turned on. The first PMOS transistor P1 and the second PMOS transistor P2 precharge the pair of local input/output lines LIO and LIOb to the level of the core voltage VCORE1 and the third PMOS transistor P3 equalizes the pair of local input/output lines LIO and LIOb.
Meanwhile, when the precharge signal LIOEQb is disabled at a logic high level, the first to third PMOS transistors P1, P2, and P3 are turned off and thus the precharged local input/output line LIO and inverted local input/output line LIOb are set to different logic levels based on the logic level of the input/output data. This causes the semiconductor memory apparatus to perform a read operation and a write operation.
When the read operation and the write operation are completed, the precharge signal LIOEQb is once again enabled at a logic low level and the first to third PMOS transistors P1, P2, and P3 are turned on, causing the pair of local input/output lines LIO and LIOb to be precharged to the level of the core voltage VCORE1.
FIG. 3 is a waveform chart illustrating the operation of the precharge circuit shown in FIG. 1.
When the precharge signal LIOEQb at the level of the core voltage VCORE1 is activated at a logic low level, the core voltage VCORE1 is applied to the pair of local input/output lines LIO and LIOb such that the pair of local input/output lines LIO and LIOb are precharged. When the precharge signal LIOEQb is disabled at a logic high level, the semiconductor memory apparatus performs a read operation and a write operation and the local input/output lines LIO and LIOb are set to different logic levels. When the read operation and the write operation are completed, the precharge signal LIOEQb is activated at a logic low level, causing the pair of local input/output lines LIO and LIOb to precharge to the level of the core voltage VCORE1.
Typically, the core voltage VCORE1 should be applied to the precharge circuit to precharge the pair of local input/output lines LIO and LIOb to the level of the core voltage VCORE1. However, when a plurality of pairs of local input/output lines LIO and LIOb are precharged simultaneously, the core voltage VCORE1 drops. Accordingly, the pairs of local input/output lines LIO and LIOb are precharged to a level lower than the level of the core voltage VCORE1. The difference between the precharge level of the pairs of local input/output lines LIO and LIOb and the level of the core voltage VCORE1 is ‘A’, as depicted in FIG. 3.
In many semiconductor memory apparatuses, a plurality of pairs of local input/output lines LIO and LIOb are precharged simultaneously, thus consuming a large amount of current. A conventional precharge circuit of the semiconductor memory apparatuses, however, is unable to supply a sufficiently large amount of current to the plurality of the pairs of local input/output lines LIO and LIOb, since the internally generated core voltage VCORE1 is not responsive enough to simultaneously supply such large amount of current. As a result, the core voltage VCORE1 drops.
When the core voltage VCORE1 drops, circuits using the core voltage VCORE1 in the semiconductor memory apparatus operate unstably.
Further, when the core voltage VCORE1 drops, the precharge level is also lowered, causing deterioration in the performance of the sense amplifier S/A, which is designed to operate in a state wherein the pairs of local input/output lines LIO and LIOb are fully precharged to the level of the core voltage VCORE1.